Pin Header Layout
The module exposes two parallel 20-pin headers spaced 0.1 inches (2.54 mm) apart — the standard breadboard pitch. P1 runs along the left edge of the board and P2 runs along the right edge. Both headers are numbered top to bottom with pin 1 closest to the USB-C connector.P1 Header — Left Side
The P1 header carries power rails, the primary UART, I2C bus 0, SPI bus 0, and general-purpose GPIO.P2 Header — Right Side
The P2 header carries the 5 V USB input rail, the 8-channel ADC, PWM outputs, the secondary UART, I2C bus 1, the hardware reset line, and additional ground references.Electrical Limits
Stay within these absolute maximum ratings to avoid damaging the microcontroller:GPIO Voltage
Maximum 3.3 V on any I/O pin. The pins are not 5 V tolerant under any condition.
Per-Pin Current
Maximum 12 mA source or sink per individual GPIO pin.
Total GPIO Current
Maximum 50 mA combined across all GPIO pins simultaneously.
Reserved Pins
GPIO34 through GPIO39 are routed internally to the wireless radio subsystem (Wi-Fi and BLE). These pins are not exposed on the headers and must not be driven or read through external connections. Attempting to configure them as user GPIO in firmware has no effect and may interfere with wireless operation.To control GPIO pins programmatically, use the
anx_gpio_set_direction, anx_gpio_write, and anx_gpio_read functions from the ANX SDK. See the Peripherals guide for interface-specific examples, and the ANX SDK API Reference for the complete GPIO function signatures.