> ## Documentation Index
> Fetch the complete documentation index at: https://launchpad.anxlabs.com/llms.txt
> Use this file to discover all available pages before exploring further.
# ANX Dev Module Pin Reference and GPIO Map
> Complete pin assignment reference for the ANX dev module: GPIO numbers, alternate functions, voltage levels, current limits, and reserved pins.
The ANX dev module uses a logical GPIO numbering scheme where each physical pin is identified by a sequential number printed on the silkscreen, and each GPIO has a corresponding logical number used in firmware calls. All I/O pins operate at **3.3 V logic** — they are not 5 V tolerant. The two 20-pin headers, P1 on the left side and P2 on the right side, give you access to all 40 pins. Pin 1 on each header is marked with a square pad and a triangle on the silkscreen for easy orientation.
Never apply more than 3.3 V to any GPIO, ADC, UART, I2C, SPI, or PWM pin. Exceeding this voltage permanently damages the microcontroller. Use a level shifter when interfacing with 5 V peripherals.
## Pin Header Layout
The module exposes two parallel 20-pin headers spaced 0.1 inches (2.54 mm) apart — the standard breadboard pitch. P1 runs along the left edge of the board and P2 runs along the right edge. Both headers are numbered top to bottom with pin 1 closest to the USB-C connector.
## P1 Header — Left Side
The P1 header carries power rails, the primary UART, I2C bus 0, SPI bus 0, and general-purpose GPIO.
| Pin # | GPIO # | Alternate Function | Notes |
| ----- | ------ | ------------------ | ------------------------------------------- |
| 1 | — | 3.3 V Power | Regulated output, max 300 mA draw |
| 2 | — | GND | Ground reference |
| 3 | GPIO0 | UART0\_TX | Primary UART transmit |
| 4 | GPIO1 | UART0\_RX | Primary UART receive |
| 5 | GPIO2 | I2C0\_SDA | I2C bus 0 data; 4.7 kΩ pull-up recommended |
| 6 | GPIO3 | I2C0\_SCL | I2C bus 0 clock; 4.7 kΩ pull-up recommended |
| 7 | GPIO4 | SPI0\_MOSI | SPI bus 0 master out |
| 8 | GPIO5 | SPI0\_MISO | SPI bus 0 master in |
| 9 | GPIO6 | SPI0\_CLK | SPI bus 0 clock |
| 10 | GPIO7 | SPI0\_CS | SPI bus 0 chip select (active low) |
| 11 | GPIO8 | — | General purpose |
| 12 | GPIO9 | — | General purpose |
| 13 | GPIO10 | — | General purpose |
| 14 | GPIO11 | — | General purpose |
| 15 | GPIO12 | — | General purpose |
| 16 | GPIO13 | — | General purpose |
| 17 | GPIO14 | — | General purpose |
| 18 | GPIO15 | — | General purpose |
| 19 | GPIO16 | — | General purpose |
| 20 | GPIO17 | — | General purpose |
## P2 Header — Right Side
The P2 header carries the 5 V USB input rail, the 8-channel ADC, PWM outputs, the secondary UART, I2C bus 1, the hardware reset line, and additional ground references.
| Pin # | GPIO # | Alternate Function | Notes |
| ----- | ------ | ------------------ | ---------------------------------------------------- |
| 1 | — | 5 V Power | USB VBUS input, not regulated — do not exceed 5.5 V |
| 2 | — | GND | Ground reference |
| 3 | GPIO18 | ADC0 | 12-bit ADC, 0–3.3 V input range |
| 4 | GPIO19 | ADC1 | 12-bit ADC, 0–3.3 V input range |
| 5 | GPIO20 | ADC2 | 12-bit ADC, 0–3.3 V input range |
| 6 | GPIO21 | ADC3 | 12-bit ADC, 0–3.3 V input range |
| 7 | GPIO22 | ADC4 | 12-bit ADC, 0–3.3 V input range |
| 8 | GPIO23 | ADC5 | 12-bit ADC, 0–3.3 V input range |
| 9 | GPIO24 | ADC6 | 12-bit ADC, 0–3.3 V input range |
| 10 | GPIO25 | ADC7 | 12-bit ADC, 0–3.3 V input range |
| 11 | GPIO26 | PWM0 | Hardware PWM channel 0 |
| 12 | GPIO27 | PWM1 | Hardware PWM channel 1 |
| 13 | GPIO28 | PWM2 | Hardware PWM channel 2 |
| 14 | GPIO29 | PWM3 | Hardware PWM channel 3 |
| 15 | GPIO30 | UART1\_TX | Secondary UART transmit |
| 16 | GPIO31 | UART1\_RX | Secondary UART receive |
| 17 | GPIO32 | I2C1\_SDA | I2C bus 1 data; 4.7 kΩ pull-up recommended |
| 18 | GPIO33 | I2C1\_SCL | I2C bus 1 clock; 4.7 kΩ pull-up recommended |
| 19 | — | RESET | Active-low hardware reset; pull low briefly to reset |
| 20 | — | GND | Ground reference |
## Electrical Limits
Stay within these absolute maximum ratings to avoid damaging the microcontroller:
Maximum **3.3 V** on any I/O pin. The pins are not 5 V tolerant under any condition.
Maximum **12 mA** source or sink per individual GPIO pin.
Maximum **50 mA** combined across all GPIO pins simultaneously.
## Reserved Pins
GPIO34 through GPIO39 are routed internally to the wireless radio subsystem (Wi-Fi and BLE). These pins are not exposed on the headers and must not be driven or read through external connections. Attempting to configure them as user GPIO in firmware has no effect and may interfere with wireless operation.
To control GPIO pins programmatically, use the `anx_gpio_set_direction`, `anx_gpio_write`, and `anx_gpio_read` functions from the ANX SDK. See the [Peripherals guide](/dev-module/peripherals) for interface-specific examples, and the ANX SDK API Reference for the complete GPIO function signatures.